The invention relates to a method of fabricating a trench capacitor. The invention relates in particular to a trench capacitor having improved leakage current properties and an associated fabrication method with simplified process steps for forming an insulation collar.
FIG. 1 is a simplified sectional view of a DRAM semiconductor memory cell with a trench capacitor in accordance with the prior art, as is disclosed for example in the Published European Patent Application No. EP 0 949 680 A2. In accordance with FIG. 1, a conventional DRAM (Dynamic Random Access Memory) semiconductor memory cell has a trench capacitor 160 formed in a substrate 101. The trench capacitor 160 essentially includes a trench 108 filled with a conductive filling material 161 as a second capacitor plate. In the vicinity of a lower region of the trench 108, a buried plate 165 is formed as a first capacitor plate in the substrate 101. The buried plate may be formed for example by diffusion from an ASG (arsenosilicate glass) layer. Situated between the buried plate 165 serving as first capacitor plate and the filling material 161 serving as second capacitor plate there is a dielectric layer 164 for lining the lower region of the trench 108 and for forming a capacitor dielectric.
Furthermore, the DRAM semiconductor memory cell has a field-effect transistor 110, which has a gate 112 and also source and drain diffusion regions 113 and 114. The diffusion regions 113 and 114 are isolated from one another by a channel 117, the diffusion region 114 being connected to the trench capacitor 160 via a contact region 125.
In order to avoid undesirable leakage currents, an insulation collar or simply collar 168 is situated on an upper region of the trench capacitor 160 or of the trench 108.
A buried well or layer 170 is situated below the surface of the substrate 101 and essentially serves as a connection between the buried plates 165 of the respective adjacent DRAM semiconductor memory cells in the memory cell array.
In order to control the respective DRAM semiconductor memory cells or the memory array, each cell has a bit line and also a word line. Usually, the gates 112 form a word line, while the diffusion region 113 is connected to a bit line 185 via a contact 183. In this case, the bit line 185 is isolated from the diffusion region by an insulating layer 189.
In accordance with FIG. 1, respectively adjacent DRAM semiconductor memory cells are isolated from one another by a shallow trench isolation (STI). A word line 120 lies not only above the actual transistor 110 but also above the trench 108. A xe2x80x9cfolded bit line architecturexe2x80x9d is thereby obtained. However, the invention described below is not restricted to an architecture of this type.
FIGS. 2A to 2C show essential method steps for forming the insulation collar 168 in accordance with the prior art. Identical reference symbols designate identical or similar elements or layers which are only described once in detail.
In accordance with FIG. 2A, firstly the trench 108 is formed in the semiconductor substrate 101 with the aid of a xe2x80x9cpad stackxe2x80x9d 107. The pad stack 107 includes, for example, a pad oxide layer 104 and a pad stop layer 105, on which a hard mask layer (not illustrated) can be superposed. An oxide layer (SiO2) or boundary layer 151 serving as an etching stop layer or barrier layer preferably has a thickness of 5 to 50 nm and can be formed by deposition or ca be formed thermally. A detailed description of the method for forming the pad stack 107 or the trench 108 is dispensed with at this point since it essentially corresponds to a conventional method.
Furthermore, in accordance with FIG. 2A, a sacrificial filling material 152, composed of polysilicon for example, is formed in a lower region of the trench 108. A coplanar insulation collar layer 167 is subsequently formed on the surface of the wafer and in the trench 108. This conformal insulation collar layer 167 or collar layer is formed for example through the use of a chemical deposition method (CVD, chemical vapor deposition), an oxide having a constant thickness of approximately 2 to 10 nm preferably being deposited. A densification is subsequently carried out in order to improve the properties of the insulation collar layer 167, the densification taking place for example at a temperature of approximately 1000xc2x0 C. in an N2 or Ar environment.
In accordance with FIG. 2B, in a subsequent method step the insulation collar layer 167 or the collar is patterned, a reactive ion etching (RIE) preferably being carried out, using CF4, CHF3 or C4F8 for example. In accordance with FIG. 2B, after this patterning step no insulation collar layer 167 remains on the pad stack 107, as a result of which the insulation collar 168 is essentially formed. During this method step, the sacrificial filling material 152 is simultaneously uncovered in the trench 108, in order thus to allow to remove the sacrificial filling material 152.
In accordance with FIG. 2C, in a subsequent method step, the sacrificial filling material 152 and the boundary layer 151 are completely removed in the lower region of the trench 108 (in particular if a thermal oxide (SiO2) and/or a deposited oxide is used as the boundary layer 151, then it can be preserved as a barrier layer in the upper region of the trench 108), which may also result in the insulation collar 168 being etched back in its upper region. In the worst-case situation during such a method step, the insulation collar 168 is etched back on its top side to such an extent that the semiconductor substrate 101 is uncovered and the substrate 101 is etched in an upper region of the trench 108. The probability of the substrate 101 being undesirably uncovered in such a way is also increased if, by way of example, the trench is extended in the lower region of the trench 108. The functioning of the DRAM semiconductor memory cell is thereby significantly impaired or completely prevented. Furthermore, with the use of vapor phase doping for forming the buried plate 165, at the uncovered silicon edge, a highly doped region can likewise be formed in an undesirable manner, such that the functioning of the semiconductor memory cell once again suffers as a result.
Since, in the method described above, the insulation collar layer 167 is completely removed from the pad stack 107, a part of the pad stack 107 is eroded in the course of a subsequent overetching process for ensuring a sufficient opening to the sacrificial filling material 152. Such erosion of the pad nitride or the pad stack 107 in the cell array and in planar support regions (not illustrated) takes place non-uniformly, which is why planarization in particular of the shallow trench isolation (STI) in subsequent process steps is made more difficult. Furthermore, a predetermined minimum thickness of the pad stack or of the pad nitride layer as etching stop layer is necessary for the shallow trench isolation or the STI oxide 180, so that an initial thickness of the pad stack or pad nitride increased by the erosion thickness is usually required. This increased pad stack thickness in turn requires a longer mask opening process for the trench 108 (deep trench mask open process), which consumes more resist, as a result of which a thicker resist layer becomes necessary. However, a thicker resist layer in turn adversely affects the process window of trench lithography, which can lead to a reduced yield.
Furthermore, the pad stack 107 can likewise be eroded during subsequent etching processes, which can once again lead to losses of yield. Moreover, in the event of facetting of the stop layer or pad nitride layer 105 (greatly tapered pad nitride layer 105 at the edge of the trench), the substrate may be uncovered above the upper insulation collar edge. Such a pad nitride facetting usually arises during a trench etching process, the selectivity of the trench etching process with respect to the hard mask decreasing toward the edge of a wafer. Therefore, the hard mask, which is intended to protect the pad nitride 105 against an etching attack, can be completely eroded during the trench etching process for trenches at the wafer edge, as a result of which xe2x80x9cpad nitride facettingxe2x80x9d arises. In the extreme case, the pad nitride layer 105 can be completely eroded (not illustrated) in the region around the trenches at the wafer edge, with the result that the silicon upper edge is completely uncovered. This can lead to the destruction of the trench structures in proximity to the surface. Silicon particles are thereby produced which are in turn distributed over the entire wafer during a subsequent wet cleaning process and which lead to enormous losses of yield.
It is accordingly an object of the invention to provide a method of fabricating a trench capacitor which overcome the above-mentioned disadvantages of the heretofore-known trench capacitors and fabrication methods of this general type such that a trench capacitor having an improved leakage current behavior and an associated fabrication method having an improved yield and a simplified and cost-effective insulation collar process is achieved.
With the foregoing and other objects in view there is provided, in accordance with the invention, a trench capacitor, including:
a substrate having a trench formed therein, the trench having an upper region and a lower region;
an insulation collar formed non-conformally in the upper region of the trench, the insulation collar having an upper section and a lower section, the insulation collar having a first layer thickness in the upper section and having a second layer thickness in the lower section, the first layer thickness being greater than the second layer thickness;
a buried plate formed adjacent to the lower region of the trench as a first capacitor plate;
a dielectric layer lining the lower region of the trench and the insulation collar as a capacitor dielectric; and
a conductive filling material filled into the trench as a second capacitor plate.
In particular by virtue of using a non-conformal insulation collar which has a larger layer thickness in an upper section of the trench than in a lower section of the trench, an improved leakage current behavior and an increased yield are obtained in conjunction with simplified process control.
Preferably, the insulation collar is formed such that it is essentially triangular, and can include one or a plurality of layers. In the case of an insulation collar including a plurality of layers, one layer may serve as a (sacrificial) protective layer with respect to subsequent etching processes.
In accordance with another feature of the invention, the insulation collar includes a plurality of layers.
In accordance with yet another feature of the invention, wherein at least one of the plurality of layers is a non-conformally formed layer.
In accordance with a further feature of the invention, the trench is a bottle-shaped trench, and the conductive filling material has a widened region with a cavity formed therein.
In accordance with another feature of the invention, the insulation collar is composed of an oxide, a nitride and/or an oxinitride.
With the objects of the invention in view there is also provided, a method for fabricating a trench capacitor, which includes the steps of:
forming a trench in a substrate;
providing a sacrificial filling material in a lower region of the trench;
forming a non-conformal layer in the trench having the sacrificial filling material in the lower region;
removing at least a part of the non-conformal layer for uncovering the sacrificial filling material;
removing the sacrificial filling material from the lower region of the trench;
forming a buried plate in the substrate adjacent to the lower region of the trench as a first capacitor plate;
forming a dielectric layer, which lines the lower region of the trench and lines an inner side of an insulation collar, as a capacitor dielectric; and
filling the trench with a conductive filling material as a second capacitor plate.
In other words, the insulation collar is preferably formed in that a non-conformal insulation collar layer is formed and at least a part of the non-conformal insulation collar layer is subsequently removed. The above described effect of pad nitride facetting at the edge of the trenches with the accompanying substrate erosion can be reliably prevented in this way. A significant simplification in the process of forming the insulation collar and the buried plate in the trench capacitor is obtained in particular in the case where at least a part of the non-conformal insulation collar layer is removed through the use of isotropic or anisotropic etching.
As an alternative, it is possible to form a conformal insulation collar layer with a superposed, non-conformal (sacrificial) protective layer, as a result of which cavities are reliably prevented from being etched free or incipiently etched in particular in the case of bottle-shaped trench capacitor structures.
A chemical deposition method (CVD), a plasma deposition method (PECVD, plasma enhanced CVD) or a chemical low-pressure deposition method (LPCVD) which is available anyway in standard processes is preferably used for forming the non-conformal insulation collar layer. Both the fabrication costs and the reliability of the trench capacitor can thereby be significantly improved.
Another mode of the invention includes the steps of forming a boundary layer on trench walls subsequent to the step of forming the trench, and removing the boundary layer in the lower region of the trench after the step of removing the sacrificial filling material.
A further mode of the invention includes the steps of forming the buried plate by using an outdiffusion from the boundary layer in the lower region of the trench.
Another mode of the invention includes the steps of forming the buried plate by using an outdiffusion from the boundary layer and concurrently densifying an insulation collar layer.
Yet another mode of the invention includes the steps of forming the buried plate by using an outdiffusion from the boundary layer and concurrently forming and densifying an insulation collar layer.
According to a further mode of the invention, the step of providing the sacrificial filling material includes filling the trench with the sacrificial filling material, and recessing (lowering) the sacrificial filling material as far as a given height.
With the objects of the invention in view there is also provided, a method for fabricating a trench capacitor, which includes the steps of:
forming a trench in a substrate;
forming a non-conformal layer in the trench;
removing at least a part of the non-conformal layer in a lower region of the trench;
forming a buried plate in the substrate adjacent to the lower region of the trench as a first capacitor plate;
forming a dielectric layer lining the lower region of the trench and lining an inner side of an insulation collar as a capacitor dielectric; and
filling the trench with a conductive filling material as a second capacitor plate.
According to another mode of the invention, the step of forming the non-conformal layer includes forming a first conformal insulation collar layer having a first thickness outside the trench, and forming a second conformal insulation collar layer having a second thickness inside the trench.
According to yet another mode of the invention, the step of forming the non-conformal layer includes forming a conformal insulation collar layer having a given thickness outside the trench, and forming a non-conformal insulation collar layer having a varying thickness inside the trench.
According to a further mode of the invention, the step of forming the non-conformal layer includes forming a conformal insulation collar layer inside and outside the trench, and forming a non-conformal sacrificial protective layer having a varying thickness at least inside the trench.
According to another mode of the invention, the step of forming the non-conformal layer includes forming a plurality of layers.
Another mode of the invention includes the step of forming the non-conformal layer and/or the sacrificial protective layer by using a deposition process such as a CVD process, a PECVD process and a LPCVD process.
According to another mode of the invention, the step of removing at least a part of the non-conformal layer is performed by an etching process such as an isotropic etching process and an anisotropic etching process.
With the objects of the invention in view there is further provided, a method for fabricating a trench capacitor, which includes the steps of:
forming a trench in a substrate;
forming a conformal insulation collar layer in the trench;
forming a sacrificial filling material in a lower region of the trench;
forming a non-conformal sacrificial protective layer in an upper region of the trench;
removing at least a part of the non-conformal sacrificial protective layer for uncovering the sacrificial filling material;
removing the sacrificial filling material from the lower region of the trench;
removing the insulation collar layer in the lower region of the trench for forming an insulation collar;
forming a buried plate in the substrate adjacent to the lower region of the trench as a first capacitor plate;
forming a dielectric layer, which lines the lower region of the trench and an inner side of the insulation collar, as a capacitor dielectric; and
filling the trench with a conductive filling material as a second capacitor plate.
According to another mode of the invention, the step of forming the sacrificial filling material includes filling the trench with the sacrificial filling material, and recessing or lowering the sacrificial filling material as far as a given height.
Another mode of the invention includes the step of forming the insulation collar layer and/or the sacrificial protective layer by using a deposition process such as a CVD process, a PECVD process or a LPCVD process.
According to another mode of the invention, the step of removing the insulation collar layer in the lower region of the trench is performed by using an isotropic etching process or an anisotropic etching process.
According to yet another mode of the invention, the step of removing at least a part of the sacrificial protective layer is performed by an isotropic etching process or an anisotropic etching process.
A further mode of the invention includes the step of forming the buried plate in a self-aligning manner with respect to the insulation collar layer.
Yet a further mode of the invention includes the step of forming the buried plate by using an outdiffusion from the sacrificial filling material.
A further mode of the invention includes the step of forming the buried plate by using a vapor phase doping.
Another mode of the invention includes the step of widening the lower region of the trench relative to an upper region of the trench for forming a bottle shape.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a trench capacitor, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.